Technical Field
The present invention generally relates to three-dimensional fin-type transistor fabrication. More particularly, the present invention relates to fabrication including removal of part of the channel for tuning FinFET performance in replacement-metal-gate (RMG) or gate-last flow.
Background Information
As semiconductor devices continues to scale down, fabrication challenges continue to mount for providing both the smaller foot print and improved performance Therefore, the 3-dimensional fin-type FET (referred to as FinFET) technology becomes widespread since 14 nm node and beyond replacing the older planar CMOS technology at 20 nm node and older.
Thus, a need continues to exist for downward scalable semiconductor fabrication techniques that improve performance.